FIG. 1 illustrates a conventional way to lay out a complementary metal oxide semiconductor (CMOS) inverter 10 on a silicon wafer, where the specific embodiment shown has a p-type transistor 12 in n-well and an n-type transistor 14 in p-doped region to give a p to n aspect ratio of 2 to 1, and where the p to n aspect ratio is split into two legs. Each p-type transistor 12 has output contacts 16 over drain 17, where the output contacts 16 serve as a terminal for both legs of transistors 12 arranged in mirror-image relationship on either side of a continuous first level interconnect or output line 20. Each n-type transistor 14 has output contacts 18 over drain 19, where output contacts 18 serve as a terminal for both legs of transistors 14, also in mirror-image relationship. A continuous first level interconnect or output line 20 connects the output contacts 16 and 18, and may be metal, such as aluminum. It is in this line 20 where electromigration problems occur.
To complete this description, the input to the inverter is along input lines 30 which function as the gates in the inverter 10, and which may be doped polysilicon. The sources 32 for p-type transistors 12 are power supply, V.sub.DD, and the sources 34 for n-type transistors 14 are ground.
With this conventional layout, unidirectional currents are present in the output node in the vicinity of the inverter. In FIG. 1, the arrows indicate the direction of current flow. When the input lines 30 are low, there is unidirectional current in the entire continuous first level interconnect or output line 20 over the p-transistor 12. When the input lines 30 are high, there is unidirectional current in the entire continuous first level interconnect or output line 20 over the n-transistor 14, as shown in FIG. 1. With this conventional layout 10, only the horizontally oriented portion of the metal output line 20 is bidirectional. For the rest of the length, oriented vertically in FIG. 1, metal output line 20 is unidirectional. That is, in the upper two-thirds over p-transistor 12 and drain 17, current only flows down output line 20 (as oriented in FIG. 1), never up; in the lower one-third over n-transistor 14 and drain 19, current also only flows down output line 20, never up. Because of the cumulative and repeated unidirectional flows of electrons in this latter portion of metal output line 20, there is repeated electromigration of the metal atoms in the direction of current flow and thus potential breakage points in the metal lines at regions 36.
S. M. Sze, ed., VLSI Technology, McGraw-Hill, New York, 1983, pp. 369-371, indicates that
"[a] prime consideration in device reliability is the electromigration resistance of the metallization. Electromigration is observed as a material transport of the conductive material. It occurs by the transfer of momentum from the electrons, moving under the influence of the electric field applied along the conductor, to the positive metal ions. Hence, after a conductor failure, a void or break in the conductor is observed and a nearby hillock or other evidence of material accumulation in the direction of the anode [Figure references omitted.] is found."
On page 370, Sze shows several SEM micrographs of breaks in metal lines. Techniques to increase electromigration resistance of aluminum film conductors include alloying with copper, incorporation of discrete layers such as titanium, encapsulating the conductor in a dielectric or incorporating oxygen during film deposition. The mean-time-to-failure (MTF) of the conductor also seems to be related to the grain size in the metal film; distribution of grain size; the degree to which the conductor exhibits fiber texture, i.e. in the &lt;111&gt; direction; method of film deposition and line width, according to Sze.
It would be helpful if other straightforward methods were discovered which reduce electromigration and increase MTF for metal and other conductors.